The present invention relates to semiconductor integrated circuits and more particularly to structures and methods for protection against charging damage, especially during fabrication of integrated circuits.
Increased performance of integrated circuits is a continual goal of integrated circuit design. Complementary metal oxide semiconductor (“CMOS”) circuits utilize both n-type field effect transistors (“NFETs”) and p-type field effect transistors (“PFETs”). Because of the different ways in which NFETs and PFETs operate, performance is most improved in CMOS circuits when conditions under which NFETs and PFETs operate are specially tailored to the unique needs of each type of transistor.
Hybrid orientation technology (“HOT”) refers to a way of manufacturing CMOS circuits in which the NFET has a longitudinal direction aligned with one crystal orientation of a semiconductor substrate and the PFET has a longitudinal direction aligned with a different crystal orientation of the substrate. Higher on-current and faster switching can be achieved in an NFET when the longitudinal direction (direction of a length of the channel region) is oriented in accordance with the <001> crystal orientation, due to the greater mobility of electrons in that crystal orientation. In addition, higher on-current and faster switching can be achieved in a PFET for which the longitudinal direction is oriented in accordance with the <110> crystal orientation, due to the greater mobility of holes in that crystal orientation. Unfortunately, the longitudinal directions of the NFET and the PFET cannot be aligned with these different crystal orientations simply by laying out the NFET and the PFET in different horizontal directions parallel to the top surface i.e., the major surface of the semiconductor substrate. The <001> crystal orientation is oriented at an angle with respect to a plane in which the <110> crystal orientation runs. Therefore, transistors having these different crystal orientations can only be achieved by forming regions of the semiconductor substrate which have different crystal orientations and fabricating the NFET and the PFET in these different regions.
Through use of bonded semiconductor-on-insulator (“SOI”) and epitaxial growth techniques, it is possible to provide semiconductor regions at the major surface of a substrate which have different crystal orientations. However, new problems arise in conductively connecting SOI transistor regions to bulk semiconductor substrate regions through epitaxial regions. These problems include greater susceptibility to electrostatic discharge damage during fabrication.
Certain processes utilized in the fabrication of semiconductor integrated circuits such as plasma etching and deposition can cause electrostatic charges to build up on metal or other conductor structures of such circuits. When unprotected, certain semiconductor devices, especially those which include thin dielectric structures, can be damaged by excessively high voltages across the dielectric structures. In particular, high voltages applied to gate conductors or semiconductor regions of field effect transistors can cause the gate dielectric layers of NFETs and PFETs to break down, rendering them inoperative.
Hybrid orientation technology (“HOT”) uses both a bulk device, e.g., transistor, and a SOI device in the same circuit. HOT contrasts with conventional technologies in which individual circuits are implemented by either using only bulk devices or by using only SOI devices. Traditionally, the bulk devices need diode protection against process induced charging damage while SOI devices are inherently robust and do not require any protection. In some circuit designs, bulk devices and SOI devices share terminals, causing new situations for charging damage to occur. For these reasons, new protection schemes become necessary for protecting devices in HOT circuits against charging damage.